The present invention relates to semiconductor devices and processing, and more particularly to a structure and method of providing a buried plate for an array of trench capacitors in a semiconductor-on-insulator chip.
Some types of semiconductor chips include capacitors that are referred to as “trench capacitors” because at least part of the capacitor is formed within a trench that extends into the interior of a semiconductor substrate. Such capacitors are advantageously used because they take up relatively little area of the surface of the substrate in relation to the amount of capacitance they provide. Trench capacitors also include a capacitor dielectric, often called a “node dielectric”, which extends along a sidewall of the trench. Frequently, one of the conductive plates of the capacitor is an inner plate provided inside the trench. Another one of the conductive plates is an outer plate extending along the sidewall of the trench on a side of the capacitor dielectric opposite the conductive plate inside the trench. Most typically, the inner plate, also referred to as a “node electrode”, is the plate on which a variable voltage is maintained from one point in time to another. The inner plate is subject to being charged or discharged during operation, while the outer plate is typically held at a constant voltage.
The outer plate is often provided as a region of doped semiconductor material in the exterior region of the substrate surrounding the trench, in which case the second conductive plate is referred to as a “buried capacitor plate” or “buried plate”. In order to maintain the buried plate at a constant voltage during operation, the buried plate must be connected through a conductive contact structure to an external source of potential. In some earlier techniques of fabricating trench capacitors, the function of the buried plate is provided by a bulk semiconductor region of the substrate which has a uniform p-type dopant concentration, in which case such conductive contact can be provided through a direct contact to any exposed surface of the bulk semiconductor region.
However, in more recent techniques, the buried plate is provided as an n-type doped region in the immediate vicinity of the sidewall of the trench, such buried plate being conductively connected to the buried plates of other trench capacitors by a laterally extending, vertically confined n-type doped region of the semiconductor substrate referred to as an “n-band.” In order to form maintain the buried plates of such trench capacitors at a constant potential, a conductive contact structure must be provided which extends from a surface of the substrate into the vertically confined n-band found below the surface.
Conventionally, the formation of a buried plate, the n-band and a conductive contact structure contacting the n-band have required a complicated and relatively expensive fabrication process. This is particularly true when trench capacitors are provided in semiconductor-on-insulator substrates, such as silicon-on-insulator (SOI) substrates. Such complicated processing is best understood with reference to the stages of processing in a prior art method illustrated in FIGS. 1 and 2. As shown in FIG. 1, an SOI substrate 10 has a plurality of trenches 12 extending downwardly from a major surface 14 of the substrate through a silicon-on-insulator (SOI) layer 16, a buried oxide layer 18, and at least somewhat into a p-type doped bulk region 20 of the substrate. An insulating dielectric 22 covers the major surface 14 of the substrate 10.
Trench capacitors are formed which extend along sidewalls of each of the trenches 12 in the following way. Trenches 12 are etched into the substrate, after which a buried plate 24 of each trench capacitor is formed within the bulk semiconductor region surrounding each trench 12 but not within the SOI layer 16 by outdiffusion of an n-type dopant from inside each trench. During such processing, the SOI layer 16 is protected from unwanted outdiffusion of the n-type dopant. Thereafter, the node dielectric 26 and node electrode 28 of each trench capacitor 30 are formed, which completes the individual trench capacitors.
However, further processing is still required to form the n-band 32 and the conductive contact structure. Typically, the n-band 32 is formed after completing the trench capacitors by implanting an n-type dopant into a vertically confined and laterally extending region of the semiconductor substrate. Such processing requires the formation of a patterned mask layer above the insulating layer 22 on the substrate, the patterned mask layer permitting a high energy ion implant to proceed into the region of the n-band 32 while at the same time protecting other portions of the semiconductor substrate from damage.
In addition, either subsequently or prior thereto, a conductive contact via 34 as shown in FIG. 2 must be formed to extend from a position at or above the major surface 14 of the substrate 10, through the SOI layer 16, the buried oxide layer 18, and into the bulk region 20 and n-band 32 that connects the buried plates 24 of the trench capacitors. The formation of the conductive contact via requires the formation and photolithographic patterning of an additional patterned mask layer, typically a hard mask layer, above the major surface 14 of the substrate. Thereafter, a contact hole is etched through the insulating layer 22, the SOI layer 16, the BOX layer 18, and into the n-band region 32 of the bulk region 20 of the substrate. Subsequently, the contact hole is filled with a conductive material such as n+ doped polysilicon to form the conductive contact structure 34. As apparent from the foregoing, not only is separate masking required to form the conductive contact structure, but a separate step is required to conductively fill the contact structure from that used to form the node electrodes 28 of the trench capacitors 30 (FIG. 1), as well as a separate step to etch back or planarize the conductive fill to the top surface of the substrate. Such methods of forming the buried plate, n-band and conductive contact structure are not only complicated, involving many dedicated processing steps, but are also expensive. The two mask levels produce difficulties relating to process control, potential misalignment of the masks, and inevitable defects resulting therefrom.
Accordingly, it would be desirable to provide a less complicated, less expensive way of forming a structure in which the buried plates of an array of trench capacitors are tied to a common potential available at a surface of the substrate.